In modern multi-processor systems that employ inclusive cache systems, processor cache memories often maintain multiple copies of data. In an inclusive cache system, when one processor alters one copy of the data, it is necessary to update or invalidate all other copies of the data which may appear elsewhere in the multi-processor system. Thus, in a system that employs an inclusive cache, to ensure coherency among the multiple copies of the data, every valid write to one copy of the data must update or invalidate all other copies of the data.